Digital Logic Lab — Gates, K-Maps & FSMs
Digital Logic Lab at /dldlab is UtilBloom’s browser Logisim-style workspace for undergrad digital logic design: place AND, OR, NOT, NAND, NOR, XOR, and XNOR gates plus inputs, LEDs, clocks, and flip-flops on a grid, wire them orthogonally, and evaluate live without uploading netlists. Derive truth tables, extract SOP/POS, minimize with Quine–McCluskey, inspect Karnaugh maps, run timing waveforms, design Moore/Mealy FSMs, and export structural or behavioral Verilog—all client-side so coursework stays on your device. Pair with Circuit Lab for analog MNA; open this lab when the problem is Boolean algebra, sequential machines, or HDL stubs.
What you can do
- Gate-level schematic capture
Drop combinational gates, constants, switches, LEDs, clocks, D/JK/T flip-flops, and SR latches; rotate, wire, and erase on a Multisim-like grid with live 0/1 highlighting.
- Live combinational evaluation
Toggle inputs and watch outputs update immediately via levelized gate evaluation with cycle detection warnings for feedback loops.
- Truth tables and Boolean forms
Exhaustively enumerate inputs (capped for performance), show output columns, and display canonical SOP/POS plus minimized expressions for each output.
- Quine–McCluskey and K-maps
Minimize covers with Quine–McCluskey, visualize 2–6 variable Karnaugh maps, and optionally replace the schematic with a synthesized gate network from the minimal SOP.
- Sequential timing
Drive clocks manually or on a timer, simulate D/JK/T flip-flops and SR latches, and plot digital timing diagrams for counters and shift registers.
- FSM designer
Edit Moore or Mealy state diagrams, derive next-state and output equations, and generate educational gate/FF netlists onto the schematic canvas.
- Verilog export
Copy structural Verilog from the netlist or behavioral FSM modules, plus optional truth-table testbench stubs for homework handoff.
- Privacy-first simulation
Evaluation, minimization, and export run entirely in the browser with localStorage persistence—nothing is uploaded for ordinary analysis.
Worked examples
Half adder live check
A,B → XOR sum, AND carry
Open /dldlab, load Half adder, toggle inputs A and B, and confirm Sum and Cout LEDs match the half-adder truth table.
Simplify an unminimized SOP
SOP simplify sample
Load SOP simplify, switch Analysis to Simplify, Run, read the minimal SOP, and optionally Apply minimized circuit.
2-bit counter timing
T FF ripple counter
Load 2-bit counter, set Timing mode, Run, and inspect Q0/Q1 waveforms across clock steps.
How it compares
Desktop Logisim, Digital, and FPGA vendor tools remain the standard for large HDL projects and FPGA bitstreams. Digital Logic Lab is the UtilBloom answer when you need a free browser DLD studio for gates, K-maps, flip-flops, FSMs, and Verilog stubs without an install. It does not synthesize to FPGA bitstreams or model gate delays in nanoseconds. For analog schematics open /circuitlab; for numeric scratch work use /scientific.
Questions
Is Digital Logic Lab the same as Logisim?
No. It is inspired by Logisim’s gate-level sandbox but is an independent UtilBloom studio with truth tables, Quine–McCluskey, K-maps, FSM design, and Verilog export in the browser.
Which devices and analyses are available?
Combinational gates, I/O, clocks, D/JK/T flip-flops, SR latches, live eval, truth tables, Boolean minimize, K-maps, timing waveforms, Moore/Mealy FSMs, and Verilog export.
Are simulations uploaded?
No. Netlist evaluation and minimization run client-side. Schematics persist in local storage on this device only.
How many inputs can a truth table handle?
Exhaustive tables are capped (around 10 inputs) so the browser stays responsive. Larger designs should be split or analyzed per output cone.
Can I export HDL?
Yes. Use the Verilog button for structural netlists or behavioral FSM modules, and optionally a testbench stub derived from the truth table.
How does this relate to Circuit Lab?
Circuit Lab solves analog MNA (DC, AC, Bode). Digital Logic Lab is the separate digital workspace. Both keep work in the tab.